Object's details: Build Testbenches for Verification in Shift Register ICs using SystemVerilog

Provider:Czasopisma PAN

Description

Title:
Build Testbenches for Verification in Shift Register ICs using SystemVerilog
Creator:
Widianto;
Chasrun, H.M.;
Lis, Robert
Contributor:
Widianto : University of Muhammadiyah Malang, Department of Electrical Engineering, Indonesia;
Chasrun, H.M. : University of Muhammadiyah Malang, Department of Electrical Engineering, Indonesia;
Lis, Robert : Wroclaw University of Science and Technology, Poland
Description:
International Journal of Electronics and Telecommunications (IJET, eISSN 2300-1933, untill 2013 also print ISSN 2081-8491) is a periodical of Electronics and Telecommunications Committee of Polish Academy of Sciences and it is published by Warsaw Science Publishers of PAS. It continues tradition of the Electronics and Telecommunications Quarterly (ISSN 0867-6747) established in 1955 as the Rozprawy Elektrotechniczne. The IJET is a scientific periodical where papers present the results of original, theoretical, experimental and reviewed works. They consider widely recognized aspects of modern electronics, telecommunications, microelectronics, optoelectronics, radioelectronics and medical electronics. The authors are outstanding scientists, well‐known experienced specialists as well as young researchers – mainly candidates for a doctor's degree. The papers present original approaches to problems, interesting research results, critical estimation of theories and methods, discuss current state or progress in a given branch of technology and describe development prospects. All the papers published in IJET are reviewed by international specialists who ensure that the publications are recognized as author's scientific output. The printed periodical is distributed among all those who deal with electronics and telecommunications in national scientific centers as well as in numeral foreign institutions, and it is subscribed by many specialists and libraries. Its electronic version is available at http://ijet.pl. The papers received are published within half a year if the cooperation between author and the editorial staff is efficient. The papers may be submitted to the editorial office by the journal web page http://ijet.pl. Journal Metrics: IMPACT FACTOR 2022: 0.7 CiteScore metrics from Scopus 2022: 1.7 SCImago Journal Rank (SJR) 2022: 0.256 Source Normalized Impact per Paper (SNIP) 2022: 0.431;
Editor-in-Chief Ryszard S. Romaniuk, Warsaw University of Technology, Institute of Electronic Systems, Poland Managing Editor Danuta Sobczak-Bartosiewicz, Warsaw University of Technology, Poland Technical Editors Grzegorz Borowik, Warsaw University of Technology, Institute of Telecommunications, Poland Maciej Linczuk, Warsaw University of Technology, Institute of Electronic Systems, Poland Secretary in-Charge Danuta Ojrzenska-Wojter, Warsaw University of Technology, Institute of Telecommunications, Poland Administrative Assistant Danuta Sobczak-Bartosiewicz, Warsaw University of Technology, Poland Technical Secretary Michał Ramotowski, Warsaw University of Technology, Poland Editorial Advisory Board Prof. Victor-Valeriu Patriciu, Director Doctoral School of Electronics, Informatics and Communications for Defense and Security, Military Technical Academy Bucharest, Romania, Romania Prof. Bart Scheers, Royal Military Academy, Belgium Dr. Eli Winjum, Norwegian Defence Research Establishment, Norway Wladyslaw Skarbek, Warsaw University of Technology, IRE, Poland Christian Napoli, University of Catania, Italy Rosario Giunta, University of Catania, Italy Christopher Chiu, University of Technology Sydney, Australia Prof. Emiliano Tramontana, University of Catania, Italy Prof Robin Braun, University of Technology Sydney, Australia Dr David Davis, University of Technology Sydney, Australia dr Brian Culshaw, University of Strathclyde, UK, United Kingdom Grzegorz Chmaj, University of Nevada, United States Giuseppe Pappalardo, University of Catania, Italy Michael Affenzeller, University of Applied Sciences Upper Austria Prof. Stavros Hatzopoulos, Laboratory of Hearing Science Audiology Dept., University of Ferrara, Italy, Italy Prof Nikita M Ryskin, Saratov State University, Russian Federation Prof. Adam Wolisz, Technische Universität Berlin, Department of Electrical Engineering and Computer Science Telecommunication Networks Prof. Edmundo Monteiro, Departamento de Engenharia Informatica Universidade de Coimbra Portugal, Portugal Prof. Zoubir Mammeri, IRIT, Université Paul Sabatier 118 Route de Narbonne F-31062 Toulouse Cedex 9 FRANCE, France Dr Paul D Polishuk, IGI, Boston, MA, USA Giuseppe Macchiarella, Politecnico di Milano,Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Italy Prof. Bernd Steinbach, Bergakademie Freiberg Fakultät für Mathematik und Informatik Institut, Germany Jan Szmidt, Warsaw University of Technology, Poland Zenon Chaczko, University of Technology Sydney, Australia Józef Modelski, Warsaw University of Technology, Poland Wiesław Woliński, Warsaw University of Technology, Poland Ryszard Klempous, Wroclaw University of Technology, Poland Radomir Stanković, University of Niš, Serbia Javier Poncela, University of Malaga, Spain Marek Turowski, CFD Research Corporation, United States Dawid Zydek, NV Energy, United States Wojciech Szpankowski, Purdue University, United States Jacek Żurada, University of Louisville, United States Tadeusz Luba, Warsaw University of Technology, Poland Stefan Hahn, Warsaw University of Technology, Poland Gilbert De Mey, Ghent University, Belgium Svetlana Yanushkevich, University of Calgary, Canada Viktor Krozer, Technical University of Denmark, Denmark Adam Morawiec, European Electronic Chips & Systems Design Initiative, France Herman Rohling, Technical University of Hamburg, Germany Franco Davoli, University of Genowa, Italy Michał Mrozowski, Gdańsk University of Technology, Poland Włodzimierz Janke, Koszalin University of Technology, Poland<;
p> Marek Amanowicz, Military University of Technology, Poland Antoni Rogalski, Military University of Technology, Poland Andrzej Materka, Technical University of Łódź, Poland Henry Selvaraj, University of Nevada, United States
Object availability:
free access
Rights:
<br><b>International Journal of Electronics and Telecommunications </b> is an open access journal with all content available with no charge in full text version. The journal content is available under the license CC BY 4.0 International <a href=" https://creativecommons.org/licenses/by/4.0/">https://creativecommons.org/licenses/by/4.0/</a>.
Date:
2022.09.06
Type:
Article
Coverage:
619-623
Publisher:
Polish Academy of Sciences Committee of Electronics and Telecommunications
Subject:
testbench;
verification;
shift register IC;
stuck-atfaults;
SystemVerilog
Identifier:
ISSN 2081-8491, eISSN 2300-1933
Data provider:
Czasopisma PAN

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Object's details: Build Testbenches for Verification in Shift Register ICs using SystemVerilog

Description

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